Hello all, PCI hardware typically uses write-posting (delaying and combining writes). The writes are committed at least when a read is performed. This is why you see many PCI drivers reading some trivial memory location in order to be sure to commit their writes to the device. This applies to pci_iomap()ed memory which physically exists at the PCI target or PCI Express end-point. However, when using coherently-cached memory (which exists in the PCI host or PCI Express root complex) which precautions must I take to make sure the device will read recent data? I.e. If I data write to the virtual address returned by dma_alloc_coherent(), what must I do to make sure the device sees this data, and not older data? Also, are wmb()s necessary to prevent re-ordering of my writes()? Regards, Leon -- To unsubscribe from this list: send an email with "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx Please read the FAQ at http://kernelnewbies.org/FAQ
