Re: IDT/Exception handling understanding - kernel vs userspace control path

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I think the answer is found in the Intel manual -
exception/trap/interrupt handling.   The answer is when any of the
three mentioned events happened, hardware will trigger the IDT into
action, and if the CPL is not the same, "stack switching" will occur.
 IDT does not have any "return address" as I have wrongly said, but a
descriptor value instead.

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