Re: [PATCH] x86: use explicit timing delay for pit accesses in kernel and pcspkr driver

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On 22-02-08 09:12, Peter Teoh wrote:

This timing of 8Mhz (or 8.33Mhz right?)

It's generally implemented as something like 7.5 to 8.33 yes, with that 8.33 being a specification figure.

is supposed to be 1/4 of the PCI bus speed of 33Mhz right?   (read from
altera website).

No. It _can_ be divided down from the PCI clock but only if it'll do. It's supposed to be at around 8 MHz, whetever the source.

And so how about 66Mhz PCI bus - so for 8 bus cycles it will be half
of 1us, correct?

No, although PCI-X system with an ISA bridge no doubt exist, any system driving an ISA bus at 16 MHz would serve mostly as an ISA peripheral cooker.

Rene.

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