Re: [PATCH] x86: use explicit timing delay for pit accesses in kernel and pcspkr driver

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Thanks again for the elaborate answer, I have learned a lot.   Just
would like to ask one more question:

On Fri, Feb 22, 2008 at 3:11 PM, Rene Herman <rene.herman@xxxxxxxxxxxx> wrote:
> On 21-02-08 17:24, Peter Teoh wrote:
>
>  Well, no, it's about address setup and timeout delays indeed and about how
>  the specifications of the ISA bus make (or made...) this a well defined and
>  CPU-speed independent way for creating those short delays. An access to a
>  non-existent port on ISA takes some 8 bus cycles for address setup and
>  timeout which with the regular ISA bus speed of 8 MHz gets us our 1 us.
>

This timing of 8Mhz (or 8.33Mhz right?) is supposed to be 1/4 of the
PCI bus speed of 33Mhz right?   (read from altera website).

And so how about 66Mhz PCI bus - so for 8 bus cycles it will be half
of 1us, correct?

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