RE: OS Clock

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> -----Original Message-----
> From: Bithika Khargharia [mailto:bithika@xxxxxxxxx] 
> Sent: 24 March 2007 05:54 PM
> To: Erik Mouw; Martyn Welch
> Cc: kernelnewbies@xxxxxxxxxxxx
> Subject: Re: OS Clock
> 
> Thank you for both of your replies. Reading these registers 
> through the CPU does not make sense as you rightly pointed 
> out. I was thinking more along the lines of a DMA kind of 
> mechanism. I know that these registers have a memory-mapped 
> area that can be used to configure them from the OS and 
> program the counters to read different events. In a similar 
> manner, if it was possible to have the counters write to some 
> other memory-mapped area one could then read the data from 
> that memory-area after the experiments are done. Is that a 
> possibility? 

I really don't see how this would work. A DMA transfer would be able to
transfer a block of contiguous data over a system bus. You are looking
at transfering a number of registers repeatedly. Even if they are
contiguously mapped, you still face the huge problem that you want to
read them every nano second (i.e. with a frequency of 1GHz). Worse than
that, you are now bringing a system bus into the equation. Even if you
could utilse the bus 100% of the time to transfer the registers in
question (i.e. not allow the CPU to use it at all - which would pretty
much rule out doing anything useful with the processor), you wouldn't
have the bandwidth to configure the operation and do the transfer under
the timing conditions you are asking for (see Eric's reply about clock
cycles, the system bus is slower...). Even if these transfers were
possible, you will still require a processor somewhere capable of
causing these transfers.

Your main problem is that 1 nanosecond is a *really* short space of
time, even for a fast microprocessor.

Martyn

----
Martyn Welch
Principal Software Engineer
Radstone Digital Processing
Part of GE Fanuc Embedded Systems

Phone: +44 (0) 1327 322748
email: martyn.welch@xxxxxxxxxxxxxx
web: www.radstone.com

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