Intel chip set IRQ routing.

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Hello,

  I have a question regarding how interrupts are routed
on Intel platforms. I am not sure whether kernelnewbies
is the right place to ask the question but I couldn't find
a mailing list that discusses intel chipset related issues.
If someone can point me there, that will be really helpful.

  My system has Intel Xeon CPU, E7520 (MCH) and
82801ER (ICH). The MCH has three PCI express ports
and is interfaced to ICH through HL1.5. A syskonnect
PCIe ethernet card is installed on one of the slots of
MCH. It don't have an IOAPIC. The ICH has the IOAPIC.

My questions are:

1.  The syskonnect driver, by default uses INTx mechanism.
I installed the driver and from /proc/interrupts, I find that
IRQ number 169 is allocated for this card. Please see
cat /proc/interrupts below:

  0:        124      88320            IO-APIC-edge  timer
  1:          0          9                 IO-APIC-edge  i8042
  8:          0          0                 IO-APIC-edge  rtc
  9:          0          0                  IO-APIC-level  acpi
14:          0       1836              IO-APIC-edge  ide0
169:          0          0               IO-APIC-level  eth2
177:          0        293             IO-APIC-level  eth0
NMI:      88671      88644 
LOC:      88257      88310 
ERR:          0
MIS:          0

  It also shows that the interrupt is delivered by the IO-APIC.
How this is possible? As I mentioned above, the only link I could
find between MCH and ICH is HL1.5. I looked into the spec
of MCH and ICH and couldn't find any specific registers that
will let the routing of interrupts from MCH to ICH IOAPIC.
(You may find the specs from the following URL:
http://www.intel.com/design/chipsets/E7520_E7320/documentation.htm)

2. Then I modified the driver and added pci_enable_msi() to use MSI
instead of INTx. At that time, I got a different IRQ (209) number

cat /proc/interrupts

           CPU0       CPU1       
  0:        124     407539    IO-APIC-edge  timer
  1:          0          9    IO-APIC-edge  i8042
  8:          0          0    IO-APIC-edge  rtc
  9:          0          0   IO-APIC-level  acpi
14:          0       1950    IO-APIC-edge  ide0
177:          0        738   IO-APIC-level  eth0
209:          0          0         PCI-MSI  eth2
NMI:     408756     408795 
LOC:     407492     407490 
ERR:          0
MIS:          0

I think I understand the reason. MSI interrupts bypass the IOAPIC and goes
directly to the LocalAPIC of the CPU (at address 0xFEExxxxx). Am I right?

Thanks.

Sadik.

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