On Wed, 29 Sep 2004 01:54:58 +0200, Michael Brennan <mbrennan@xxxxxxxx> wrote: > On Tuesday 28 September 2004 22.49, Timur Tabi wrote: > > Michael Brennan wrote: > > > error_code: > > > pushl %ds > > > pushl %eax > > > xorl %eax, %eax > > > pushl %ebp > > > pushl %edi > > > pushl %esi > > > pushl %edx > > > decl %eax # eax = -1 > > > pushl %ecx > > > pushl %ebx > > > > > > My question is why the 'decl %eax' is 4 lines after the clearing of eax > > > 'xorl %eax %eax'. Can't it just be put right after xorl? > > > > It's for CPU pipeline optimization. > > ok. i see. > > Can anyone tell me where I can read more about optimizing for pipelining? I > searched the internet and looked in the intel specifications, but I only find > explanations on how the pipelining and prefetching works, not how to optimize > for it. http://webster.cs.ucr.edu/AoA/Linux/HTML/CPUArchitecturea3.html#1014785 just knowing how pipelining and prefetching works will bring you a long way. > > Could someone at least tell me how the optimization works in this example? (if > its not far too complex, then I'll forget about it) there's time for the xor to finish before %eax is accessed again, so that there isn't a pipeline stall. > > /Michael > > > > > -- > Kernelnewbies: Help each other learn about the Linux kernel. > Archive: http://mail.nl.linux.org/kernelnewbies/ > FAQ: http://kernelnewbies.org/faq/ > > -- Brandon Niemczyk http://bniemczyk.doesntexist.com -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
