Hello While working on an embedded board design, we came across the following question: Let's say, we have a CPU, RAM and a PCI-bridge on the local bus. On the PCI-bus we have a bus-master capable device. Let's say, that device drives a long burst-transfer. The PCI-bus is fully loaded, but, since the local bus is much (about 3 times in our case) faster, than the PCI-bus, there are windows, where CPU gets access to the local bus. Then, during one of such windows the CPU tries to read a couple of registers from PCI. Now come our assumptions: 1) because the PCI-bus is busy, the CPU doesn't come through to read those registers, so, it is put in the wait state, right? 2) in principle it would be a dead-lock - CPU waits for PCI, but the current PCI-master has come to a point of requesting the local bus, which is used by the CPU, so, it doesn't get a grant... 3) A possible solution would be, that the PCI bridge notices, that it doesn't get the local bus, and aborts the burst-transfer. Is it really resolved that way, or somehow otherwise, or not resolved at all?:-)) Thanks Guennadi --------------------------------- Guennadi Liakhovetski, Ph.D. DSA Daten- und Systemtechnik GmbH Pascalstr. 28 D-52076 Aachen Germany -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
