Regards,
Ameet
Nir Tzachar wrote:
On Thu, Jan 01, 2004 at 08:51:35AM +0200, Nir Tzachar wrote:
those generally fall apart if the cpu also has a cpu store buffer and a weakly ordered memory model ;)
if you referred to one of the mentioned algorithms, can you please explain?
a cpu with a store buffer and a weakly ordered memory model will not have
it's writes to memory visible to other cpus without explicit
synchronisation......
ok, got it. but hey, if ur cpu has a store buffer or uses a weakly ordered memory model, then you also got some synchronization primitives, (ie; memory barriers, which can be used to implement a higher synchronization primitive) no? otherwise, the cpu manufacturer has done a pretty bad job....
anyway, if his cpu does not implement any synchronization primitives, then he got a uni-processor box (very likely.. ), and all his problems can be solved with one of these algorithms.
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nir.
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