On Thu, Jan 01, 2004 at 08:51:35AM +0200, Nir Tzachar wrote: > > those generally fall apart if the cpu also has a cpu store buffer and a > > weakly ordered memory model ;) > if you referred to one of the mentioned algorithms, can you please explain? a cpu with a store buffer and a weakly ordered memory model will not have it's writes to memory visible to other cpus without explicit synchronisation......
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