* Scott Foulk <foulk@firinn.com> [2003-04-23 22:03]: > How does this lock the bus when the instruction is reg to reg, aka > intra-processor? > > > "If a memory operand is referenced, the LOCK# signal is automatically > asserted for the duration of the exchange operation..." > > So I don't think the bus is locked on this one. > > Imagine the reason why a bus LOCK# is asserted. LOCK#s make only sense if memory locations can be accessed by different components concurrently, i.e. really at the same time. For example, an SMP system with shared memory. But memory within a processor as registers are can only be accessed by the processor that owns this memory. Thus, it wouldn't make sense conceptually if a LOCK# was asserted for a reg-reg operation that cannot be interrupted. Any comments are welcome. wbr, Lukas -- Lukas Ruf | Wanna know anything about raw | <http://www.lpr.ch> | IP? <http://www.rawip.org> | -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
