How does this lock the bus when the instruction is reg to reg, aka intra-processor? I have to check my Intel Instruction Set Reference. Okay, I checked my Pentium Developers Manual, Intel publ. order # 242691-001, pg. 11-389 [1996 so may have changed]: XCHG "If a memory operand is referenced, the LOCK# signal is automatically asserted for the duration of the exchange operation..." So I don't think the bus is locked on this one. On Tue, 2003-04-22 at 01:49, Bryan K. wrote: > In intel documentation I 've seen that the instruction nop is an alias for > xchg %eax, %eax which is implicitly a LOCK instruction. This means that if > one cpu does nops the others cannot access the bus? Have I missed something? > > _________________________________________________________________ > Add photos to your e-mail with MSN 8. Get 2 months FREE*. > http://join.msn.com/?page=features/featuredemail > > -- > Kernelnewbies: Help each other learn about the Linux kernel. > Archive: http://mail.nl.linux.org/kernelnewbies/ > FAQ: http://kernelnewbies.org/faq/ > -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
