On Tue, 29 Oct 2002 00:15:47 -0800
Seth Arnold <sarnold@wirex.com> wrote:
> On Tue, Oct 29, 2002 at 03:02:09PM +0800, ??? wrote:
> > how about the hyperthreading tech ? , i am still use the p2-550.
>
> Sorry; only p4-based chips can do hyperthreading, and not all p4s have
> it enabled. Check www.intel.com for details on the p4 family of cpus.
>
> Note that there is some level of argument whether hyperthreading is
> actually a gain -- it is similar to sharing a single cache among two
> cpus -- cutting in half the amount of cache available to each pretend
> processor.
I think hyperthreading (as in P4 or Cray MTA) is fundamentally
different from dual-core CPUs (like Power4). AFAIK, hyperthreaded CPUs
share the functional units, unlike (?) Power4, which share the L2 cache.
One can make the analogy with the way modern (from the last 40
years) operating systems do I/O (R=run, B=block for IO, W=wakeup):
thr1 R------B W R------B
thr2 ---B W------B
i.e. by overlapping processing with waiting for IO completion. Now
replace IO with "memory RW/cache-miss".
The pure RR-scheduled version of the above would be (assuming time slice
is 10 dashes long):
thr1 R------B W R------B
thr2 ---B++++++ W R------B++
The ``+'' are the wasted cycles, i.e. there *is* a runnable
CPU/process, but it is not scheduled, because the current CPU/process
time quanta is not expired yet. Of course the total time does not
increse with the number of wasted cycles, because there are times when
no CPU/process is runnable.
~velco
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