The patch titled
x86: calgary: increase max PHB number
has been added to the -mm tree. Its filename is
x86-calgary-increase-max-phb-number.patch
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------------------------------------------------------
Subject: x86: calgary: increase max PHB number
From: "Darrick J. Wong" <djwong@xxxxxxxxxx>
Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so
bump the limits up and provide an explanation of the requirements for each
class.
Signed-off-by: Darrick J. Wong <djwong@xxxxxxxxxx>
Acked-by: Muli Ben-Yehuda <muli@xxxxxxxxxx>
Cc: Ingo Molnar <mingo@xxxxxxx>
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: "H. Peter Anvin" <hpa@xxxxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>
---
arch/x86/kernel/pci-calgary_64.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff -puN arch/x86/kernel/pci-calgary_64.c~x86-calgary-increase-max-phb-number arch/x86/kernel/pci-calgary_64.c
--- a/arch/x86/kernel/pci-calgary_64.c~x86-calgary-increase-max-phb-number
+++ a/arch/x86/kernel/pci-calgary_64.c
@@ -103,11 +103,14 @@ int use_calgary __read_mostly = 0;
#define PMR_SOFTSTOPFAULT 0x40000000
#define PMR_HARDSTOP 0x20000000
-#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS 8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
-#define PHBS_PER_CALGARY 4
+/*
+ * The maximum PHB bus number.
+ * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+ * x3950M2: 4 chassis, 48 PHBs per chassis = 192
+ * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
+ * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
+ */
+#define MAX_PHB_BUS_NUM 384
/* register offsets in Calgary's internal register space */
static const unsigned long tar_offsets[] = {
_
Patches currently in -mm which might be from djwong@xxxxxxxxxx are
x86-calgary-increase-max-phb-number.patch
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