On Thu, 13 Dec 2018, Daniel Schwierzeck wrote: > > I'm not so sure, if overwriting 0x80000000 (default value of EBase on > > this SoC) with the exception handler is allowed. Is this address "zero" > > handled somewhat specific in MIPS Linux? AFAICT, the complete DDR > > area on my platform (0x8000.0000 - 0x87ff.ffff) is available for Linux. > > So allocating some memory for this exception handler seems the right > > way to go to me. > > > > maybe that's why some platforms define a load address of 0x80002000 or similar > to protect this area somehow. It is. MIPS processors before r2 (i.e. r1 and all the legacy ones) did not have the CP0.EBase register and the (non-CP0.Status.BEV) exception vector base was hardwired to 0x80000000 or 0xffffffff80000000 for 32-bit and 64-bit implementations respectively. Then bootstrap/console monitor firmware typically used some RAM right above the exception handler area for its own purposes. Consequently the load address of any executable to be run by such firmware had to be set such as to avoid clobbering these areas. HTH, Maciej
