Hello Matthias Schiffer,
The patch af2d1b521bfb: "MIPS: ath79: add support for QCA953x QCA956x
TP9343" from Jul 20, 2018, leads to the following static checker
warning:
arch/mips/ath79/clock.c:570 qca956x_clocks_init()
warn: mask and shift to zero
arch/mips/ath79/clock.c:588 qca956x_clocks_init()
warn: mask and shift to zero
arch/mips/ath79/clock.c
554 pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
555 out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
556 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
557 ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
558 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
559
560 pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
561 nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
562 QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
563 hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
564 QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This is 0x1fff
565 lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
566 QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
567
568 cpu_pll = nint * ref_rate / ref_div;
569 cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
570 cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
^^^^^^^^^^^
But 0x1fff >> 13 is zero.
571 cpu_pll /= (1 << out_div);
572
573 pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
574 out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
575 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
576 ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
577 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
578 pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
579 nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
580 QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
581 hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
582 QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
583 lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
584 QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
585
586 ddr_pll = nint * ref_rate / ref_div;
587 ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
588 ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
^^^^^^^^^^^
Same
589 ddr_pll /= (1 << out_div);
590
591 clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
592
593 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
594 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
regards,
dan carpenter
