Hello!
On 07/20/2018 02:58 PM, John Crispin wrote:
> From: Felix Fietkau <nbd@xxxxxxxx>
>
> ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
> need to be a multiple of 4.
>
> Cc: Alban Bedel <albeu@xxxxxxx>
> Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
> Signed-off-by: Felix Fietkau <nbd@xxxxxxxx>
> Signed-off-by: John Crispin <john@xxxxxxxxxxx>
> ---
> arch/mips/ath79/common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
> index fad32543a968..cd6055f9e7a0 100644
> --- a/arch/mips/ath79/common.c
> +++ b/arch/mips/ath79/common.c
> @@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
>
> void ath79_ddr_wb_flush(u32 reg)
> {
> - void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
> + void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
Parens not needed, the operator priorities are natural.
[...]
MBR, Sergei
