Le mer. 11 juil. 2018 à 14:18, Vinod <vkoul@xxxxxxxxxx> a écrit :
On 10-07-18, 17:45, Paul Cercueil wrote:
Le lun. 9 juil. 2018 à 19:14, Vinod <vkoul@xxxxxxxxxx> a écrit :
> On 03-07-18, 14:32, Paul Cercueil wrote:
> > The JZ4725B has one DMA core starring six DMA channels.
> > As for the JZ4770, each DMA channel's clock can be enabled with
> > a register write, the difference here being that once started,
it
> > is not possible to turn it off.
>
> ok so disable for this, right..
>
> > @@ -204,6 +205,8 @@ static inline void
> > jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma,
> > {
> > if (jzdma->version == ID_JZ4770)
> > jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn));
> > + else if (jzdma->version == ID_JZ4725B)
> > + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn));
>
> but you are writing to a different register here..
Yes. SoCs >= JZ4770 have the DCKE read-only register, and
DCKES/DCKEC to
set/clear bits in DCKE.
On JZ4725B, DCKE is read/write, but the zeros written are ignored
(at least
that's what the
documentation says).
and that was not documented in the log... so i though it maybe a typo.
Right, I will add a comment in-code to explain that it's normal.
--
~Vinod
Thanks,
-Paul
