On Sun, Jun 03, 2018 at 11:02:01PM +0900, Tokunori Ikegami wrote:
> The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as below.
>
> R10: PCIe Transactions Periodically Fail
>
> Description: The BCM5300X PCIe does not maintain transaction ordering.
> This may cause PCIe transaction failure.
> Fix Comment: Add a dummy PCIe configuration read after a PCIe
> configuration write to ensure PCIe configuration access
> ordering. Set ES bit of CP0 configu7 register to enable
> sync function so that the sync instruction is functional.
> Resolution: hndpci.c: extpci_write_config()
> hndmips.c: si_mips_init()
> mipsinc.h CONF7_ES
>
> This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX.
> Also the dummy PCIe configuration read is already implemented in the Linux
> BCMA driver.
> Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
> too so that the sync instruction is externalised.
>
> Signed-off-by: Tokunori Ikegami <ikegami@xxxxxxxxxxxxxxxxxxxx>
> Reviewed-by: Paul Burton <paul.burton@xxxxxxxx>
> Acked-by: Hauke Mehrtens <hauke@xxxxxxxxxx>
> Cc: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
> Cc: Rafał Miłecki <zajec5@xxxxxxxxx>
> Cc: linux-mips@xxxxxxxxxxxxxx
I presume this patch is ready to apply now (thanks for the reviews
folks).
How far back does this need backporting to stable branches?
It applies easily back to 3.14 I think (commit 3c06b12b046e ("MIPS:
BCM47XX: fix position of cpu_wait disabling")), but you mentioned other
fixes too. Have those been backported too, and if not is there any point
backporting this?
Thanks
James
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