Hi Paul-san, Thanks for your reviewing and advices. > Could this be moved to platform-specific code, in order to avoid the > platform-specific #ifdef in generic code? > > For example, this would seem like a good fit for the existing > bcm47xx_cpu_fixes() function. I have just fixed this by v3 patch series so please review again. Regards, Ikegami > -----Original Message----- > From: Paul Burton [mailto:paul.burton@xxxxxxxx] > Sent: Thursday, May 31, 2018 8:10 AM > To: IKEGAMI Tokunori > Cc: James Hogan; PACKHAM Chris; Hauke Mehrtens; Rafa~B Mi~Becki; > linux-mips@xxxxxxxxxxxxxx > Subject: Re: [PATCH v2 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core > ExternalSync for BCM47XX PCIe erratum > > Hi Tokunori, > > On Mon, May 28, 2018 at 09:24:51AM +0900, Tokunori Ikegami wrote: > > diff --git a/arch/mips/kernel/cpu-probe.c > b/arch/mips/kernel/cpu-probe.c > > index cf3fd549e16d..75039e89694f 100644 > > --- a/arch/mips/kernel/cpu-probe.c > > +++ b/arch/mips/kernel/cpu-probe.c > > @@ -427,8 +427,18 @@ static inline void check_errata(void) > > * making use of VPE1 will be responsable for that VPE. > > */ > > if ((c->processor_id & PRID_REV_MASK) <= > PRID_REV_34K_V1_0_2) > > - write_c0_config7(read_c0_config7() | > MIPS_CONF7_RPS); > > + set_c0_config7(MIPS_CONF7_RPS); > > break; > > +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE > > + case CPU_74K: > > + /* > > + * BCM47XX Erratum "R10: PCIe Transactions Periodically > Fail" > > + * Enable ExternalSync for sync instruction to take effect > > + */ > > + pr_info("ExternalSync has been enabled\n"); > > + set_c0_config7(MIPS_CONF7_ES); > > + break; > > +#endif > > Could this be moved to platform-specific code, in order to avoid the > platform-specific #ifdef in generic code? > > For example, this would seem like a good fit for the existing > bcm47xx_cpu_fixes() function. > > Thanks, > Paul
