This series fixes a race condition during in TLB exceptions for I6400 & I6500 CPUs where TLB RAMs are shared between threads/VPs within a core, and implements a few optimisations & cleanups for TLB exception handling. Applies atop v4.12-rc3. Paul Burton (6): MIPS: Add CPU shared FTLB feature detection MIPS: Handle tlbex-tlbp race condition MIPS: Allow storing pgd in C0_CONTEXT for MIPSr6 MIPS: Use current_cpu_type() in m4kc_tlbp_war() MIPS: tlbex: Use ErrorEPC as scratch when KScratch isn't available MIPS: tlbex: Remove struct work_registers arch/mips/Kconfig | 2 +- arch/mips/include/asm/cpu-features.h | 41 ++++++ arch/mips/include/asm/cpu.h | 4 + arch/mips/kernel/cpu-probe.c | 11 ++ arch/mips/mm/tlbex.c | 234 +++++++++++++++++------------------ 5 files changed, 169 insertions(+), 123 deletions(-) -- 2.13.0
