In systems that include a MIPS Coherency Manager, the icache always
fills from a cache which is coherent across all CPUs. In I6400 & I6500
systems the icache fills from the dcache which is coherent across all
CPUs. In all other CM-based systems the icache fills from the L2 cache
which is shared between all cores.
This means that an icache will always see stores from remote CPUs
without needing to write them back any further than that L2, which is
what the cpu_icache_snoops_remote_store feature is used to test. In
order for it to return 1 without needing a per-platform override (which
is what Malta has relied upon so far) set the MIPS_IC_SNOOPS_REMOTE flag
when a CM is present.
Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
---
arch/mips/mm/c-r4k.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 3fe99cb271a9..6c1b982196eb 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1501,6 +1501,14 @@ static void probe_pcache(void)
if (c->dcache.flags & MIPS_CACHE_PINDEX)
c->dcache.flags &= ~MIPS_CACHE_ALIASES;
+ /*
+ * In systems with CM the icache fills from L2 or closer caches, and
+ * thus sees remote stores without needing to write them back any
+ * further than that.
+ */
+ if (mips_cm_present())
+ c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
+
switch (current_cpu_type()) {
case CPU_20KC:
/*
--
2.13.0
