Re: [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C

To: Binbin Zhou <zhoubb@xxxxxxxxxx>, Ralf Baechle <ralf@xxxxxxxxxxxxxx>, James Hogan <james.hogan@xxxxxxxxxx>
Subject: Re: [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C
From: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
Date: Thu, 30 Mar 2017 12:50:55 +0300
Cc: John Crispin <john@xxxxxxxxxxx>, "Steven J . Hill" <Steven.Hill@xxxxxxxxxx>, Aurelien Jarno <aurelien@xxxxxxxxxxx>, Fuxin Zhang <zhangfx@xxxxxxxxxx>, Zhangjin Wu <wuzhangjin@xxxxxxxxx>, Kelvin Cheung <keguang.zhang@xxxxxxxxx>, Yang Ling <gnaygnil@xxxxxxxxx>, 谢致邦 <Yeking@xxxxxxxxx>, linux-mips@xxxxxxxxxxxxxx, HuaCai Chen <chenhc@xxxxxxxxxx>
In-reply-to: <1490841889-13450-2-git-send-email-zhoubb@lemote.com>
References: <1490841889-13450-1-git-send-email-zhoubb@lemote.com> <1490841889-13450-2-git-send-email-zhoubb@lemote.com>
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Hello!

On 3/30/2017 5:44 AM, Binbin Zhou wrote:

As we all know, the Loongson-1 series CPUs(1A/1B/1C) share the same PRID macro.
so I rename them for more readable.


   "Better readability", perhaps?

Signed-off-by: Binbin Zhou <zhoubb@xxxxxxxxxx>
Signed-off-by: HuaCai Chen <chenhc@xxxxxxxxxx>

[...]

MBR, Sergei

Follow-Ups:
- Re: [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C
  - From: Yang Ling

References:
- [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support
  - From: Binbin Zhou
- [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C
  - From: Binbin Zhou