On 07/12/2016 21:04, Dan Carpenter wrote:
> Hello John Crispin,
>
> The patch d41ced01f21d: "MIPS: lantiq: implement support for FALCON
> soc" from Apr 19, 2012, leads to the following static checker warning:
>
> arch/mips/lantiq/falcon/sysctrl.c:152 falcon_gpe_enable()
> warn: mask and shift to zero
>
> arch/mips/lantiq/falcon/sysctrl.c
> 140 /* enable the ONU core */
> 141 static void falcon_gpe_enable(void)
> 142 {
> 143 unsigned int freq;
> 144 unsigned int status;
> 145
> 146 /* if if the clock is already enabled */
> 147 status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
> 148 if (status & (1 << (GPPC_OFFSET + 1)))
> 149 return;
> 150
> 151 freq = (status_r32(STATUS_CONFIG) &
> 152 GPEFREQ_MASK) >>
> 153 GPEFREQ_OFFSET;
>
> The mask is 0xC0 and we >> 10 which means that freq is always zero.
>
> 154 if (freq == 0)
> 155 freq = 1; /* use 625MHz on unfused chip */
>
> So we always use 625MHz.
>
> 156
> 157 /* apply new frequency */
> 158 sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
> 159 freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
> 160 udelay(1);
> 161
> 162 /* enable new frequency */
> 163 sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
> 164 udelay(1);
> 165 }
>
> regards,
> dan carpenter
>
Hi Dan,
thanks, I've added Hauke in CC. he works for Lantiq and has been taking
care of the code recently.
John
