On Wed, 11 May 2016, Florian Fainelli wrote: > >>> Applied - but "MIPS: Separate XPA CPU feature into LPA and MVH" causes > >>> a massive conflict with Florian's RIXI patches > >>> > >>> [3/6] MIPS: Allow RIXI to be used on non-R2 or R6 core > >>> [4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe > >>> [5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI > >>> > >>> I figured unapplying those three, applying Paul's series then re-applying > >>> Florian's patch on top of the whole series will be the easier path as in > >>> leaving me with the smaller rejects to manage. > >> > >> Did you already push that to mips-for-linux-next? I can give it a quick > >> spin once you do so. > > > > I just pushed a tree with everything applied. HEAD of tree is > > 22702a86997c5aed2e479bfe0b24d10d66b09604 dated May 11 11:58:06; a version > > from earlier today was broken. > > Boot tested on BMIPS5000 (BCM7425): > > Tested-by: Florian Fainelli <f.fainelli@xxxxxxxxx> NB it's not that the RIXI feature first appeared only with the MIPS32r2 ISA. It was introduced with the SmartMIPS ASE as a part of the original MIPS32r1 ISA. And similarly there's no separate RIXI config register bit provided for MIPS32r1 SmartMIPS processors, the presence of the feature is implied solely by the Config3.SM (SmartMIPS) bit, so your implementation looks like the right direction to me. Thanks for your contribution! Maciej
