Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs

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To: Florian Fainelli <f.fainelli@xxxxxxxxx>
Subject: Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
From: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Date: Wed, 10 Feb 2016 10:22:16 +0100
Cc: linux-mips@xxxxxxxxxxxxxx, blogic@xxxxxxxxxxx, cernekee@xxxxxxxxx, jon.fraser@xxxxxxxxxxxx, pgynther@xxxxxxxxxx, paul.burton@xxxxxxxxxx, ddaney.cavm@xxxxxxxxx
In-reply-to: <20160210092033.GB10352@linux-mips.org>
User-agent: Mutt/1.5.24 (2015-08-30)

On Wed, Feb 10, 2016 at 10:20:33AM +0100, Ralf Baechle wrote:

> And why do both MFC0 and MTC0 instructions above have the same opcode?

Forget this one, I should occasionally open my eyes in the morning ;)

  Ralf

Follow-Ups:
- Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
  - From: Maciej W. Rozycki

References:
- [PATCH 0/6] MIPS: BMIPS: RIXI and workarounds support
  - From: Florian Fainelli
- [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
  - From: Florian Fainelli
- Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
  - From: Ralf Baechle

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