On Tue, Feb 09, 2016 at 12:55:49PM -0800, Florian Fainelli wrote:
> +static void bmips5000_pref30_quirk(void)
> +{
> + __asm__ __volatile__(
> + " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
> + " lui $9, 0x0100\n"
> + " or $8, $9\n"
> + /* disable "pref 30" on buggy CPUs */
> + " lui $9, 0x0800\n"
> + " or $8, $9\n"
> + " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
> + : : : "$8", "$9");
> +}
Simpler:
#define read_c0_horse_with_no_name(val) __read_32bit_c0_register($22, 8, val)
#define write_c0_horse_with_no_name(val) __write_32bit_c0_register($22, 8)
...
write_c0_horse_with_no_name(read_c0_horse_with_no_name() | 0x123);
And why do both MFC0 and MTC0 instructions above have the same opcode?
Also the selector number used above for both instructions is 8 - but the
architecture only allows for 8 selectors 0..7.
Ralf
