[RFC v3 02/14] MIPS: ath79: use clk-ath79.c driver for AR913X/AR933X

[Antony Pavlov <antonynpavlov@xxxxxxxxx>]

Signed-off-by: Antony Pavlov <antonynpavlov@xxxxxxxxx>
Cc: Gabor Juhos <juhosg@xxxxxxxxxxx>
Cc: Alban Bedel <albeu@xxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
---
 arch/mips/ath79/clock.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index eb5117c..8a287bf 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -24,6 +24,7 @@
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include "common.h"
+#include "machtypes.h"
 
 #define AR71XX_BASE_FREQ	40000000
 #define AR724X_BASE_FREQ	5000000
@@ -133,6 +134,10 @@ static void __init ar913x_clocks_init(void)
 	u32 freq;
 	u32 div;
 
+	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
+		return;
+	}
+
 	ref_rate = AR913X_BASE_FREQ;
 	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
 
@@ -167,6 +172,10 @@ static void __init ar933x_clocks_init(void)
 	u32 freq;
 	u32 t;
 
+	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
+		return;
+	}
+
 	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 		ref_rate = (40 * 1000 * 1000);
@@ -483,8 +492,6 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
 
 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
 #endif
-- 
2.6.2