Coherence Manager 3 (CM3) as present in I6400 can fill icache lines effectively from dirty dcaches, so there is no need to flush dirty lines from dcaches through to L2 prior to icache invalidation. Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc evaluates to true, which avoids those dcache flushes. Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> Cc: Leonid Yegoshin <leonid.yegoshin@xxxxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx --- arch/mips/mm/c-r4k.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index fc7289dfaf5a..69e7e5873af3 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1311,6 +1311,7 @@ static void probe_pcache(void) break; case CPU_ALCHEMY: + case CPU_I6400: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; -- 2.4.10
