These patches allow I6400 core to avoid dcache flushes when making recently modified data available to icache. I6400 effectively can fill icache from dirty dcache contents, which means cpu_has_ic_fills_f_dc can evaluate to true (see patch 2). However there are a couple of bugs in the cache handling when cpu_has_ic_fills_f_dc, which need fixing first (see patch 1). That the CPU fills icache from dcache does not imply that the icache is coherent with dcache. Stale lines still need flushing from the icache, even if lines in the dcache don't need writing back first. James Hogan (2): MIPS: c-r4k: Sync icache when it fills from dcache MIPS: I6400: Icache fills from dcache arch/mips/mm/c-r4k.c | 12 ++++++++++-- arch/mips/mm/init.c | 2 +- 2 files changed, 11 insertions(+), 3 deletions(-) Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> Cc: Leonid Yegoshin <leonid.yegoshin@xxxxxxxxxx> Cc: Manuel Lauss <manuel.lauss@xxxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx -- 2.4.10
