On Tue, Jan 12, 2016 at 12:42:14AM +0000, Maciej W. Rozycki wrote: > > > Programming notes: > > > The WAIT instruction should be executed while interrupts are disabled > > > by the IE bit in the Status register. This avoids a potential timing > > > hazard, which occurs if an interrupt is taken between testing the counter > > > and executing the WAIT instruction. In this hazard case, the interrupt > > > will have been completed before the WAIT instruction is executed, so > > > the processor will remain indefinitely in wait state until the next > > > interrupt. > > > > Note that this is the opposite restriction than many older MIPS CPUs > > where it is undefined if an interrupt will restart execution of > > instructions if interrupts are disabled. So this might be a violation > > of the architecture specification. However I rather have it the BMIPS > > way than the other way ... > > It's been implementation-dependent since MIPSr1 whether a non-enabled > interrupt breaks out of WAIT, so no architecture specification violation > here. I probably should have clarified that in the commit message but alas too late, this commit is long upstream. Ralf
