On Mon, Oct 19, 2015 at 11:44:24AM -0700, Petri Gynther wrote: > BCM7425 CPU Interface Zephyr Processor, pages 5-309 and 5-310 > BCM7428B0 CPU Interface Zephyr Processor, pages 5-337 and 5-338 > > WAIT instruction: > Thread enters wait state. No instructions are executed until an > interrupt occurs. The processor's clocks are stopped if both threads > are in idle mode. > > Description: > Execution of this instruction puts the thread into wait state, an idle > mode in which no instructions are fetched or executed. The thread remains > in wait state until an interrupt occurs that is not masked by the > interrupt mask field in the Status register. Then, if interrupts are > enabled by the IE bit in the Status register, the interrupt is serviced. > The ERET instruction returns to the instruction following the WAIT > instruction. If interrupts are disabled, the processor resumes executing > instructions with the next sequential instruction. > > Programming notes: > The WAIT instruction should be executed while interrupts are disabled > by the IE bit in the Status register. This avoids a potential timing > hazard, which occurs if an interrupt is taken between testing the counter > and executing the WAIT instruction. In this hazard case, the interrupt > will have been completed before the WAIT instruction is executed, so > the processor will remain indefinitely in wait state until the next > interrupt. Note that this is the opposite restriction than many older MIPS CPUs where it is undefined if an interrupt will restart execution of instructions if interrupts are disabled. So this might be a violation of the architecture specification. However I rather have it the BMIPS way than the other way ... Ralf
