Ensure the update to which core the core-other GCR regions reflect has taken place before any core-other GCRs are accessed by placing a memory barrier (sync instruction) between the write to the core-other registers and any such GCR accesses. Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx> --- arch/mips/kernel/mips-cm.c | 6 ++++++ arch/mips/kernel/mips-cpc.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index fef2647..485e441 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -278,6 +278,12 @@ void mips_cm_lock_other(unsigned int core, unsigned int vp) } write_gcr_cl_other(val); + + /* + * Ensure the core-other region reflects the appropriate core & + * VP before any accesses to it occur. + */ + mb(); } void mips_cm_unlock_other(void) diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c index 8af4d62..566b8d2 100644 --- a/arch/mips/kernel/mips-cpc.c +++ b/arch/mips/kernel/mips-cpc.c @@ -76,6 +76,12 @@ void mips_cpc_lock_other(unsigned int core) spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core), per_cpu(cpc_core_lock_flags, curr_core)); write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF); + + /* + * Ensure the core-other region reflects the appropriate core & + * VP before any accesses to it occur. + */ + mb(); } void mips_cpc_unlock_other(void) -- 2.5.3
