Re: [PATCH 2/6] clk: pistachio: Fix override of clk-pll settings from boot loader

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Govindraj,

On Thu, Aug 6, 2015 at 6:43 AM, Govindraj Raja
<govindraj.raja@xxxxxxxxxx> wrote:
> From: Zdenko Pulitika <zdenko.pulitika@xxxxxxxxxx>
>
> Pll enable callbacks are overriding PLL mode (int/frac) and
> Noise reduction (on/off) settings set by the boot loader which
> results in the incorrect clock rate.

Please be consistent about how "PLL" is written out.  Since it's an
acronym, it should be in caps.

> PLL mode and noise reduction are defined by the DSMPD and DACPD bits
> of the pll control register. Pll .enable() callbacks enable pll
> by deasserting all power-down bits of the pll control register,
> including DSMPD and DACPD bits, which is not necessary since
> these bits don't actually enable/disable pll.
>
> This commit fixes the problem by removing DSMPD and DACPD bits
> from the "pll enable" mask.
>
> Signed-off-by: Zdenko Pulitika <zdenko.pulitika@xxxxxxxxxx>
> Signed-off-by: Govindraj Raja <govindraj.raja@xxxxxxxxxx>

Otherwise,

Reviewed-by: Andrew Bresitcker <abrestic@xxxxxxxxxxxx>




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