From: Zdenko Pulitika <zdenko.pulitika@xxxxxxxxxx>
This commit sets operating mode of fractional pll based on
the value of the fractional divider. Currently it assumes that
the pll will always be configured in fractional mode which may not be
the case. This may result in the wrong output frequency.
Signed-off-by: Zdenko Pulitika <zdenko.pulitika@xxxxxxxxxx>
Signed-off-by: Govindraj Raja <govindraj.raja@xxxxxxxxxx>
---
drivers/clk/pistachio/clk-pll.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/pistachio/clk-pll.c b/drivers/clk/pistachio/clk-pll.c
index 8802b2e..eb91748 100644
--- a/drivers/clk/pistachio/clk-pll.c
+++ b/drivers/clk/pistachio/clk-pll.c
@@ -112,6 +112,20 @@ static inline u32 pll_frac_get_mode(struct clk_hw *hw)
return val ? PLL_MODE_INT : PLL_MODE_FRAC;
}
+static inline void pll_frac_set_mode(struct clk_hw *hw, u32 mode)
+{
+ struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
+ u32 val;
+
+ val = pll_readl(pll, PLL_CTRL3);
+ if (mode == PLL_MODE_INT)
+ val |= PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD;
+ else
+ val &= ~(PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD);
+
+ pll_writel(pll, val, PLL_CTRL3);
+}
+
static struct pistachio_pll_rate_table *
pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,
unsigned long fout)
@@ -245,6 +259,12 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
pll_writel(pll, val, PLL_CTRL2);
+ /* set operating mode */
+ if (params->frac)
+ pll_frac_set_mode(hw, PLL_MODE_FRAC);
+ else
+ pll_frac_set_mode(hw, PLL_MODE_INT);
+
if (enabled)
pll_lock(pll);
--
1.9.1
