On 06/02/2015 05:12 AM, Luc Van Oostenryck wrote:
On Tue, Jun 02, 2015 at 11:08:35AM +0100, Paul Burton wrote:
I think this would read better as something like:
If a processor does not implement the lightweight sync operations then
the architecture requires that they interpret the corresponding sync
instructions as the typical heavyweight "sync 0". Therefore this
should be safe to enable on all CPUs implementing release 2 or
later of the MIPS architecture.
Is it really the case for release 2?
I'm asking because recently I needed to do something similar and I couldn't
find this garantee in the revision 2.00 of the manual.
Yes. MD00086/MD00084/MD00087 Rev 2.60 are technically MIPS R2. And this
revision explicitly lists optional codes and it has a clear statement:
Implementations that do not use any of the non-zero values of stype to
define different barriers, such as ordering bar-
riers, must make those stype values act the same as stype zero.
(don't blame me that Rev 2.60 is 5 years after initial 2.00, it is still
MIPS R2).
- Leonid.
