On Tue, 19 May 2015, James Hogan wrote: > - tlb_read_hazard > Between tlbr and mfc0 (various TLB registers). This is copied from > tlbw_use_hazard in all cases on the assumption that tlbr has similar > data writer characteristics to tlbw, and mfc0 has similar data user > characteristics to loads and stores. Be careful with this assumption, it does not stand for R4600/R4700 and R5000 processors (4 vs 3 intervening instructions), you need an extra NOP for them. Likewise there is a difference with the 5K (1 vs 0 intervening instructions), but it's already buried in our pessimistic barrier that assumes 4 intervening instructions. Maciej
