Re: [PATCH 8/9] clk: pistachio: Add sanity checks on PLL configuration

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
<ezequiel.garcia@xxxxxxxxxx> wrote:
> From: Kevin Cernekee <cernekee@xxxxxxxxxxxx>
>
> When setting the PLL rates, check that:
>
>  - VCO is within range
>  - PFD is within range
>  - PLL is disabled when postdiv is changed
>  - postdiv2 <= postdiv1
>
> Signed-off-by: Kevin Cernekee <cernekee@xxxxxxxxxxxx>
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@xxxxxxxxxx>

Reviewed-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>





[Index of Archives]     [Linux MIPS Home]     [LKML Archive]     [Linux ARM Kernel]     [Linux ARM]     [Linux]     [Git]     [Yosemite News]     [Linux SCSI]     [Linux Hams]

  Powered by Linux