On Malta, the RTC is forced into binary coded decimal (BCD) mode during
init, even if the bootloader put it into binary mode (as YAMON does).
This can result in the RTC seconds being an invalid BCD (e.g.
0x1a..0x1f) for up to 6 seconds.
In a future patch we want to take seconds into account when estimating
the frequency, however that would treat a transition from the invalid
BCD 0x1f (calculated as 25) to BCD 0x20 (20) as -5 seconds, which is
wrapped to 55 seconds and results in a very underestimated frequency.
Therefore read-modify-write the control register so that the previous
mode is preserved instead of being forced into BCD mode. This avoids the
possibility of invalid BCD values immediately afterwards.
Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Cc: Paul Burton <paul.burton@xxxxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
---
arch/mips/mti-malta/malta-time.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 185e68261f45..a030d41eb5a1 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -165,14 +165,18 @@ unsigned int get_c0_compare_int(void)
static void __init init_rtc(void)
{
+ unsigned char ctrl = CMOS_READ(RTC_CONTROL);
+
/* stop the clock whilst setting it up */
- CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
+ ctrl |= RTC_24H | RTC_SET;
+ CMOS_WRITE(ctrl, RTC_CONTROL);
/* 32KHz time base */
CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
/* start the clock */
- CMOS_WRITE(RTC_24H, RTC_CONTROL);
+ ctrl &= ~RTC_SET;
+ CMOS_WRITE(ctrl, RTC_CONTROL);
}
void __init plat_time_init(void)
--
2.3.6
