On Tue, 12 May 2015, Ralf Baechle wrote: > On systems with multiple types of FPUs this would also result in a > more consistent behaviour when a process is scheduled between different > CPUs. Hmm, do we support SMP systems where individual FPUs (or CPUs, for that matter) are different significantly enough to matter? E.g. anyhow beyond FIR[15:0], that the relevant machine instructions read directly from hardware where implemented anyway (and likewise FCSR). I think eventually we should migrate properties that have to be uniform across all the CPUs in a SMP system outside the per-CPU `cpu_data' array and have a single global copy only. This will include the ISA level, some options like the exception and cache model (not the particular topology though), VM size, etc. I think this FPU (and also MSA, specifically `msa_id') stuff will belong there as well, unless proven otherwise. That is unless we have a mixed system really available in the first place (QEMU does not count, sorry) or one is at least is being considered, and then we actually want to support it beyond finding the common set of features across all the CPUs and limiting userland to using them only (well, if limiting would at all be possible, that is, via appropriate knobs requiring privilege to control). Maciej
