Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA I/O.

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On 02/23/2015 08:24 PM, Maciej W. Rozycki wrote:
> On Mon, 23 Feb 2015, Leonid Yegoshin wrote:
> 
>> The same is basically for transfer D$ --> I$ because in MIPS it is done via L2
>> or memory.
> 
>  The original issue aside (I don't want to dive into it) this I believe is 
> left to an implementer's discretion and there are MIPS implementations 
> indeed that fill I$ directly from D$; IIRC Alchemy silicon and its 
> descendants.
> 
>   Maciej
> 
I am tracking down even more HIGHMEM bugs, so I will rework these
patches, clean-up commit messages and post again. Thanks for all the
feedback.

Steve





[Index of Archives]     [Linux MIPS Home]     [LKML Archive]     [Linux ARM Kernel]     [Linux ARM]     [Linux]     [Git]     [Yosemite News]     [Linux SCSI]     [Linux Hams]

  Powered by Linux