Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA I/O.

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On Mon, 23 Feb 2015, Leonid Yegoshin wrote:

> The same is basically for transfer D$ --> I$ because in MIPS it is done via L2
> or memory.

 The original issue aside (I don't want to dive into it) this I believe is 
left to an implementer's discretion and there are MIPS implementations 
indeed that fill I$ directly from D$; IIRC Alchemy silicon and its 
descendants.

  Maciej





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