From: "Steven J. Hill" <Steven.Hill@xxxxxxxxxx>
Build set and clear macros for the PageGrain register.
Signed-off-by: Steven J. Hill <Steven.Hill@xxxxxxxxxx>
---
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/kernel/cpu-probe.c | 2 +-
arch/mips/mm/tlb-r4k.c | 6 +++---
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 5e4aef3..45b996b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1894,6 +1894,7 @@ __BUILD_SET_C0(config5)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(pagegrain)
__BUILD_SET_C0(brcm_config_0)
__BUILD_SET_C0(brcm_bus_pll)
__BUILD_SET_C0(brcm_reset)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f56e53b..da2a78d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -540,7 +540,7 @@ static void decode_configs(struct cpuinfo_mips *c)
if (cpu_has_rixi) {
/* Enable the RIXI exceptions */
- write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
+ set_c0_pagegrain(PG_IEC);
back_to_back_c0_hazard();
/* Verify the IEC bit is set */
if (read_c0_pagegrain() & PG_IEC)
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index e90b2e8..b2afa49 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -485,11 +485,11 @@ static void r4k_tlb_configure(void)
* Enable the no read, no exec bits, and enable large virtual
* address.
*/
- u32 pg = PG_RIE | PG_XIE;
#ifdef CONFIG_64BIT
- pg |= PG_ELPA;
+ set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA);
+#else
+ set_c0_pagegrain(PG_RIE | PG_XIE);
#endif
- write_c0_pagegrain(pg);
}
temp_tlb_entry = current_cpu_data.tlbsize - 1;
--
1.7.10.4
