RE: [PATCH RFC v2 19/70] MIPS: Use the new "ZC" constraint for MIPS R6

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Maciej W. Rozycki <macro@xxxxxxxxxxxxxx> writes:
> On Fri, 16 Jan 2015, Markos Chandras wrote:
> 
> > GCC versions supporting MIPS R6 use the ZC constraint to enforce a
> > 9-bit offset for MIPS R6. We will use that for all MIPS R6 LL/SC
> > instructions.
> >
> > Cc: Matthew Fortune <Matthew.Fortune@xxxxxxxxxx>
> > Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
> > ---
> >  arch/mips/include/asm/compiler.h | 10 +++++++++-
> >  1 file changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/mips/include/asm/compiler.h
> b/arch/mips/include/asm/compiler.h
> > index c73815e0123a..8f8ed0245a09 100644
> > --- a/arch/mips/include/asm/compiler.h
> > +++ b/arch/mips/include/asm/compiler.h
> > @@ -16,12 +16,20 @@
> >  #define GCC_REG_ACCUM "accum"
> >  #endif
> >
> > +#ifdef CONFIG_CPU_MIPSR6
> > +/*
> > + * GCC uses ZC for MIPS R6 to indicate a 9-bit offset although
> > + * the macro name is a bit misleading
> > + */
> > +#define GCC_OFF12_ASM() "ZC"
> > +#else
> >  #ifndef CONFIG_CPU_MICROMIPS
> >  #define GCC_OFF12_ASM() "R"
> >  #elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
> >  #define GCC_OFF12_ASM() "ZC"
> >  #else
> >  #error "microMIPS compilation unsupported with GCC older than 4.9"
> > -#endif
> > +#endif /* CONFIG_CPU_MICROMIPS */
> > +#endif /* CONFIG_CPU_MIPSR6 */
> >
> >  #endif /* _ASM_COMPILER_H */
> 
>  I'd prefer to have a GCC version trap here just like with the microMIPS
> constraint.  What is the first upstream version to support R6?  5.0?

Correct.
 
>  Also rather than stating that the name of the macro has now become a
> misnomer I think it should actually be renamed to something more general,
> like `GCC_OFF_SMALL_ASM' (any better suggestions are welcome).  That'd
> have to be a separate patch though, to be applied first, preferably.

The ZC constraint is suitable for use in LL/SC/PREF/CACHE for all ISAs. I
believe this is the smallest width displacement for a memory operation in
all ISAs. The only other reduced displacement in Release 6 is for copro 2
load/stores which are 11-bit rather than 9-bit.

Matthew




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