RE: [PATCH RFC v2 67/70] MIPS: kernel: process: Do not allow FR=0 on MIPS R6

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Markos Chandras <Markos.Chandras@xxxxxxxxxx> writes:
> diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
> index b732c0ce2e56..41ebd5d0ac30 100644
> --- a/arch/mips/kernel/process.c
> +++ b/arch/mips/kernel/process.c
> @@ -581,6 +581,10 @@ int mips_set_process_fp_mode(struct task_struct
> *task, unsigned int value)
>  	if ((value & PR_FP_MODE_FRE) && !cpu_has_fre)
>  		return -EOPNOTSUPP;

There is an inconsistency here in that the kernel will not support
emulating FRE mode when there is no FPU but will emulate FR1 or FR0
when there is no FPU.

For consistency I think we should do this for FRE:

 	if ((value & PR_FP_MODE_FRE) && cpu_has_fpu && !cpu_has_fre)
 		return -EOPNOTSUPP;

thanks,
Matthew

> 
> +	/* FR = 0 not supported in MIPS R6 */
> +	if (!(value & PR_FP_MODE_FR) && cpu_has_fpu && cpu_has_mips_r6)
> +		return -EOPNOTSUPP;
> +
>  	/* Save FP & vector context, then disable FPU & MSA */
>  	if (task->signal == current->signal)
>  		lose_fpu(1);
> --
> 2.2.1





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