On 12/19/2014 04:43 PM, Leonid Yegoshin wrote:
On 12/19/2014 04:33 PM, David Daney wrote:From: David Daney <david.daney@xxxxxxxxxx> The two patches reverted here break eXecute-Inhibit (XI) memory protection support. Before the patches we get SIGSEGV when attempting to execute in non-executable memory, after the patches we loop forever in handle_tlbl. It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think the most prudent thing is to revert these patches, and then only reapply something that works after it has been well tested. David Daney (2): Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions" Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" arch/mips/include/asm/mipsregs.h | 1 - arch/mips/kernel/cpu-probe.c | 9 --------- arch/mips/kernel/traps.c | 7 ------- arch/mips/mm/tlbex.c | 4 ++-- 4 files changed, 2 insertions(+), 19 deletions(-)Well, it may be have sense just to fix tlb_init() instead.
I have more confidence in going back to a working configuration. My simple tests on OCTEON tell me that it is working again.
Somebody adding working support for C0_Pagegrain[PG_IEC] would want to do much more testing across many different CPUs to be able to assert that it was tested and working.
I would be happy to test any patches adding this support on a variety of different OCTEON CPU cores, but I don't have access to anything MIPS/img may have that supports this feature.
David Daney.
