On 12/18/2014 07:10 PM, David Daney wrote:
> On 12/18/2014 07:09 AM, Markos Chandras wrote:
>> From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
>>
>> Latest versions of QEMU added support for mips32r6-generic and
>> mips64r6-generic cpu types so add related definitions in preparation
>> of MIPS R6 support.
>>
>> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
>> Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
>> ---
>> arch/mips/include/asm/cpu.h | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
>> index dfdc77ed1839..23a5dbc0ee06 100644
>> --- a/arch/mips/include/asm/cpu.h
>> +++ b/arch/mips/include/asm/cpu.h
>> @@ -93,6 +93,7 @@
>> * These are the PRID's for when 23:16 == PRID_COMP_MIPS
>> */
>>
>> +#define PRID_IMP_QEMUR6 0x0000
>
> Why not have a value for a real R6 CPU, and then have QEMU emulate that?
because qemu does not implement real r6 cores at the moment. It uses
mips{32,64}r6-generic in order to get a minimal r6 core and that cpu
uses IMP=0. so that's the only thing we can use at the moment.
--
markos
