On Wed, Dec 03, 2014 at 02:37:29PM +0100, Ralf Baechle wrote: > On Tue, Jun 03, 2014 at 12:29:17PM +0200, Lars Persson wrote: > > > Good point. Would adding !cpu_has_ic_fills_f_dc as an extra condition in set_pte_at be sufficient to address your concern ? > > Returning to this old thread ... > > cpu_has_ic_fills_f_dc means a CPU's data cache does not need to be > written back to secondary cache or memory when instructions have been > updated in memory. In other words a CPU can refill the I-cache from > the D-cache on an I-cache miss. > > Only the Alchemy cores have this handy property. > > The flag is also being set for XL? CPUs in > > arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h > > but not anywhere in the probe code of arch/mips/mm/c-r4k.c which might > stil be correct - but it's at least a bit sloppy and suspicious so I'm > wondering if it's correct indeed. Jayachandran? On XLR/XLP, L1 Dcache is coherent and L1 Icache is not. We don't need to flush dcache when we change an executable page or range, just an icache flush is sufficient. At least in c-r4k.c, setting cpu_has_ic_fills_f_dc did what we needed. There were 2 issues, one is the usage in copy_to_user_page, for which a patch was posted http://patchwork.linux-mips.org/patch/6122/ (we are using this patch). Another is that we might need a "sync" before the icache flush. JC.
