On Thu, Nov 13, 2014 at 12:05:37AM -0600, Steven J. Hill wrote:
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 1559360..076e660 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1595,8 +1595,17 @@ early_param("cca", cca_setup);
>
> static void coherency_setup(void)
> {
> - if (cca < 0 || cca > 7)
> - cca = read_c0_config() & CONF_CM_CMASK;
> + if (cca < 0 || cca > 7) {
> + /*
> + * Set CCA to non-coherent to ensure that the UP kernel
> + * behaves properly even on MC processors where the ROM
> + * may have prepared the C0 registers for SMP operation.
> + */
> + if (!config_enabled(CONFIG_SMP))
> + cca = _CACHE_CACHABLE_NONCOHERENT >> _CACHE_SHIFT;
> + else
> + cca = read_c0_config() & CONF_CM_CMASK;
> + }
NAK. This would trigger falsely on pretty much every SMP platform in
MIPS history except Octeon - with usually fatal consequences.
Is there a performance disadvantage or why is this desirable?
Ralf
