From: Markos Chandras <markos.chandras@xxxxxxxxxx>
In case the YAMON bootloader is being used, it will set the Config0/K0
value to 0x5 if a multicore processor is detected. This may have
undesired effects if a CM is present since certain cache operations
may broadcast and go through the CM even if we run a UP kernel.
Therefore it's best to ensure that we are in non coherent mode
in UP kernels even if CM is present.
Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
Signed-off-by: Steven J. Hill <Steven.Hill@xxxxxxxxxx>
---
arch/mips/mm/c-r4k.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1559360..076e660 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1595,8 +1595,17 @@ early_param("cca", cca_setup);
static void coherency_setup(void)
{
- if (cca < 0 || cca > 7)
- cca = read_c0_config() & CONF_CM_CMASK;
+ if (cca < 0 || cca > 7) {
+ /*
+ * Set CCA to non-coherent to ensure that the UP kernel
+ * behaves properly even on MC processors where the ROM
+ * may have prepared the C0 registers for SMP operation.
+ */
+ if (!config_enabled(CONFIG_SMP))
+ cca = _CACHE_CACHABLE_NONCOHERENT >> _CACHE_SHIFT;
+ else
+ cca = read_c0_config() & CONF_CM_CMASK;
+ }
_page_cachable_default = cca << _CACHE_SHIFT;
pr_debug("Using cache attribute %d\n", cca);
--
1.7.10.4
